Along with the development of semiconductor technology, various memories are invented. Via Read-Only Memory (Via-ROM) records data by vias. Please refer to FIG. 1, which shows an example a Via-ROM 900. The via-ROM 900 includes a plurality of word lines WL9, a plurality of bit lines BL9 and a plurality of memory cells, such as code-0 cells C90 and code-1 cells C91. The source of the code-0 cell C90 is connected to the ground, a via at the drain of the code-0 cell C90 is conducted, and the read voltage of the code-0 cell C90 is ground. The source of the code-1 cell C91 is connected to the ground, a via at the drain of the code-1 cell C91 is opened, and the read voltage of the code-1 cell C91 is high.
The read voltage of one selected code-1 cell C91 may be dropped due to the bit-line leakages happened on the other code-0 cells C90. If a large number of code-0 cells C90 are formed on one bit line, the read voltage of the code-1 cell C91 on this bit line may be greatly dropped and cannot be accurately identified.
Especially, the bit-line leakages are easily happened at high speed via-ROM or high temperature environment and the read voltage of the code-1 cell C91 cannot be accurately identified. Therefore, how to compensate the read voltage under the bit-line leakage is an important issue nowadays.